High speed design for division & modulo operations
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United States of America Patent
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Issued Date -
Jun 28, 2012
app pub date -
Feb 11, 2008
filing date -
Nov 9, 2007
priority date (Note) -
Abandoned
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Abstract
Techniques for efficiently performing division and modulo operations in a programmable logic device. In one set of embodiments, the division and modulo operations are synthesized as one or more alternative arithmetic operations, such as multiplication and/or subtraction operations. The alternative arithmetic operations are then implemented using dedicated digital signal processing (DSP) resources, rather than non-dedicated logic resources, resident on a programmable logic device. In one embodiment, the programmable logic device is a field-programmable gate array (FPGA), and the dedicated DSP resources are pre-fabricated on the FPGA. Embodiments of the present invention may be used in Ethernet-based network devices to support the high-speed packet processing necessary for 100G Ethernet, 32-port (or greater) trunking, 32-port/path (or greater) load balancing (such as 32-path ECMP), and the like.
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