ESD clamp with auto biasing under high injection conditions
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United States of America Patent
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Issued Date -
Jun 21, 2012
app pub date -
Dec 17, 2010
filing date -
Dec 17, 2010
priority date (Note) -
Abandoned
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Abstract
In a dual direction ESD protection circuit formed from multiple base-emitter fingers that include a SiGe base region, and a common sub-collector region, the I-V characteristics are adjusted by including P+ regions to define SCR structures that are operable to sink positive and negative ESD pulses, and adjusting the layout and distances between regions and the number of regions.
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