SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF
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United States of America Patent
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Issued Date -
Jun 14, 2012
app pub date -
Mar 3, 2011
filing date -
Dec 9, 2010
priority date (Note) -
Abandoned
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Abstract
A semiconductor package is provided. The package includes a package substrate with a first surface and a second surface on the opposite side, and a plurality of via sets connecting vertically the first surface with the second surface, said via sets having a plurality of micro vias and filled with conductive material. The micro vias are grouped together, and the distance between micro vias in the via set is smaller than the distance between neighboring via sets.
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