SYSTEM-LEVEL EMULATION/VERIFICATION SYSTEM AND SYSTEM-LEVEL EMULATION/VERIFICATION METHOD
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United States of America Patent
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Issued Date -
Jun 7, 2012
app pub date -
Dec 5, 2010
filing date -
Dec 5, 2010
priority date (Note) -
Abandoned
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Abstract
A system-level emulation/verification system includes an operating device for using a simulator to set soft intellectual properties (soft IPs) corresponding to a System-on-Chip (SOC) design module, executing a simulation corresponding to the SOC design module, and using a transactor to interact with the simulator via an Application Programming Interface (API); and a hard-wired based platform, including a hard IP corresponding to a soft IP of the SOC design module, wherein the hard-wired based platform sets the hard IP according to a setting of the SOC design module, and outputs an operating result of the hard IP corresponding to the setting of the SOC design module. The hard-wired based platform executes an IP model proxy for receiving an output of the transactor, transmitting the output to the hard-wired platform for controlling the operation of the hard IP, and transmitting the operating result to the transactor executed by the operating device.
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