Selective seed layer treatment for feature plating
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United States of America Patent
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Apr 22, 2014
Grant Date -
Jun 7, 2012
app pub date -
Dec 2, 2010
filing date -
Dec 2, 2010
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Abstract
Conventional metallization processes fail at high density or small feature size patterns. For example, during patterning dry films may collapse or lift-off resulting in short circuits or open circuits in the metallization pattern. An exemplary method for metallization of integrated circuits includes forming features such as trenches, pads, and planes in a dielectric layer and depositing and selectively treating a seed layer in desired features of the dielectric layer. The treated regions of the seed layer may be used as a seed for electroless deposition of conductive material, such as copper, into the features. When the seed layer is a catalytic ink, the seed layer may be treated by curing the catalytic ink with a laser.
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