FLASH MEMORY APPARATUS
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United States of America Patent
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Issued Date -
May 17, 2012
app pub date -
Nov 12, 2010
filing date -
Nov 12, 2010
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A flash memory apparatus including a command analysis unit, a first flash memory and a second flash memory is provided. The command analysis unit with a plurality of command buffers receives a plurality of command elements and queues the command elements in the command buffers in sequence. The command analysis unit transmits the command elements simultaneously to the first flash memory and the second flash memory through a command bus, and the flash memory device writes/reads the first flash memory and the second flash memory simultaneously through a first data bus and a second data bus different from the first data bus respectively to execute an operation. The flash memory device queues the command elements so as to enhance the command throughput, and the flash memories share the same command bus for dual channel operation.
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