SELF-ALIGNED CONTACT STRUCTURE TRENCH JFET
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United States of America Patent
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Issued Date -
May 3, 2012
app pub date -
Oct 29, 2010
filing date -
Oct 29, 2010
priority date (Note) -
Abandoned
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Abstract
According to one embodiment, a self-aligned trench structure junction gate field-effect transistor (JFET) includes a silicon substrate, two or more trenches having a P-type polysilicon gate region near a bottom portion of the trench and an interlayer dielectric layer (ILDL) above the P-type polysilicon gate region, a channel region separating each trench including epitaxial silicon, an N+ source region above the channel region extending between a top of each trench, and a source metal above the N+ source region. In another embodiment, a self-aligned trench structure JFET includes a silicon substrate, two or more trenches having an N-type polysilicon gate region near a bottom portion of the trench and an ILDL above the N-type polysilicon gate region, a channel region separating each trench including epitaxial silicon, a P+ source region above the channel region extending between a top of each trench, and a source metal above the P+ source region.
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