CHIP STACKED STRUCTURE
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United States of America Patent
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N/A
Issued Date -
Apr 12, 2012
app pub date -
Mar 28, 2011
filing date -
Oct 8, 2010
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A chip stacked structure is provided. The chip stacked structure includes a first die and a second die stacked on the first die. The first die has a plurality of connection structures each which has a through hole, a connection pad and a solder bump. The connection pad has a terminal connected to the through hole. The solder bump is disposed on the connection pad and located around the through hole. The second die has a plurality of through holes which are aligned and bonded to the solder bump respectively. The chip stacked structure may simplify the process and improve the process yield rate.
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