FLIP-CHIP BONDING METHOD TO REDUCE VOIDS IN UNDERFILL MATERIAL

Number of patents in Portfolio can not be more than 2000

United States of America Patent

APP PUB NO 20120077312A1
SERIAL NO

13050538

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Abstract

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Disclosed is a flip-chip bonding method to reduce voids in underfill material. A substrate with connecting pads is provided. At least a chip with a plurality of bumps is bonded on the substrate and then an underfill material is formed between the chip and the substrate. Finally, the substrate is placed in a pressure oven in which a positive pressure greater than one atm is provided, meanwhile, the underfill material is thermally cured with exerted pressures to reduce bubbles or voids trapped inside the underfill material to avoid popcorn issues due to CTE mismatch between the chip and the substrate. In one embodiment, another underfill material is further formed between a plurality of chips and bubbles or voids trapped between the chips are also reduced by the pressurized curing.

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Patent Owner(s)

Patent OwnerAddress
WALTON ADVANCED ENGINEERING INC18 NORTH FIRST ROAD K E P Z KAOHSIUNG R O C

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Yung-Hsiang Kaohsiung, TW 186 2102
Chiu, Wen-Chun Kaohsiung, TW 9 56
LEE, Kuo-Yuan Kaohsiung, TW 13 97
Lin, Kao-Hsiung Kaohsiung, TW 1 12

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