Non-Volatile Memory System with Modified Memory Cells
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United States of America Patent
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Issued Date -
Mar 8, 2012
app pub date -
Sep 2, 2010
filing date -
Sep 2, 2010
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A method and system in which an embedded memory is fabricated in accordance with a conventional logic process includes one or more non-volatile memory cells, each having an access transistor and a capacitor, which share a common floating gate electrode. The coupling capacitor is provided with a dielectric layer having a thickness greater than the dielectric layer of the access transistor. Regions under the capacitor are implanted with a high dose implant to form an electrically shorted doped area in the channel region of the capacitor. The high dose implant improves the coupling ratio of the capacitor and enhances the uniformity of the capacitor's oxide layer.
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Cited Art Landscape
Patent Citation Ranking
- 8 Citation Count
- H01L Class
- 3.37 % this patent is cited more than
- 13 Age