METHOD FOR INTEGRATING DRAM AND NVM

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United States of America Patent

APP PUB NO 20120040504A1
SERIAL NO

12853450

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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The present invention discloses a method for integrating DRAM and NVM, which comprises steps: sequentially forming on a portion of surface of a DRAM semiconductor substrate a first gate insulation layer and a first gate layer functioning as a floating gate; and implanting ion into regions of the semiconductor substrate, which are at two sides of the first gate insulation layer, to form two heavily-doped areas that are adjacent to the first gate insulation layer and respectively function as a drain and a source; respectively forming over the first gate layer a second gate insulation layer and a second gate layer functioning as a control gate. The present invention not only increases the transmission speed but also reduces the power consumption, the fabrication cost and the package cost.

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Patent Owner(s)

Patent OwnerAddress
YIELD MICROELECTRONICS CORP7F-2 NO 28 TAI YUEN ST CHU-PEI CITY HSIN-CHU COUNTY

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
FAN, YA-TING HSINCHU COUNTY, TW 12 22
LIN, HSIN CHANG HSINCHU COUNTY, TW 15 102
TAI, CHIA-HAO HSINCHU COUNTY, TW 7 16
YANG, MING-TSANG HSINCHU COUNTY, TW 7 75
YEN, YANG-SEN HSINCHU COUNTY, TW 4 14

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