REDUCED HARDWARE MULTIPLIER
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United States of America Patent
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N/A
Issued Date -
Dec 22, 2011
app pub date -
Nov 15, 2005
filing date -
Nov 15, 2005
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
The invention is directed to a multiplication apparatus or arrangement comprising: an address unit being adapted to receive address words from an external system, which address words have a first part comprising a first number X and a second part comprising a second number Y; a memory area comprising M×M memory cells arranged to be addressed by said address words, wherein a cell addressed by a particular address word is provided with the product P of the first and second number X and Y; and an output unit arranged to provide products P from the memory area to an external system. The invention is characterized in that the cells in the memory area addressed by address words wherein Y
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