HIERARCHICAL BUFFERED SEGMENTED BIT-LINES BASED SRAM

Number of patents in Portfolio can not be more than 2000

United States of America Patent

APP PUB NO 20110305099A1
SERIAL NO

13105806

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A semiconductor memory device is disclosed. In one aspect, the device includes memory blocks with memory cells connected to a local bit-line, each local bit-line being connectable to a global bit-line for memory readout. There are also pre-charging circuitry for pre-charging the bit-lines and a read buffer for discharging the global bit-line during a read operation. The local bit-lines are pre-charged to a predetermined first voltage substantially lower than the supply voltage (VDD) of the memory device. A segment buffer is provided between each local bit-line and an input node of the respective read buffer. The segment buffer activates the read buffer during the read operation upon occurrence of a discharge on the connected local bit-line.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
IMECKAPELDREEF 75 LEUVEN 3001
KATHOLIEKE UNIVERSITEIT LEUVENLEUVEN LEUVEN FLEMISH BRABANT
STICHTING IMEC NEDERLAND5656 AE EINDHOVEN

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ashouei, Maryam Eindhoven, NL 5 42
Catthoor, Francky Temse, BE 72 1709
Cosemans, Stefan Mol, BE 27 139
Dehaene, Wim Kessel-Lo, BE 23 246
Huisken, Jos Waalre, NL 5 63
Sharma, Vibhu Leuven, BE 31 268

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation