HIERARCHICAL BUFFERED SEGMENTED BIT-LINES BASED SRAM
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United States of America Patent
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Issued Date -
Dec 15, 2011
app pub date -
May 11, 2011
filing date -
May 12, 2010
priority date (Note) -
Abandoned
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Abstract
A semiconductor memory device is disclosed. In one aspect, the device includes memory blocks with memory cells connected to a local bit-line, each local bit-line being connectable to a global bit-line for memory readout. There are also pre-charging circuitry for pre-charging the bit-lines and a read buffer for discharging the global bit-line during a read operation. The local bit-lines are pre-charged to a predetermined first voltage substantially lower than the supply voltage (VDD) of the memory device. A segment buffer is provided between each local bit-line and an input node of the respective read buffer. The segment buffer activates the read buffer during the read operation upon occurrence of a discharge on the connected local bit-line.
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