ELECTRICALLY CONNECTING ROUTES OF SEMICONDUCTOR CHIP PACKAGE CONSOLIDATED IN DIE-ATTACHMENT
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United States of America Patent
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Issued Date -
Dec 15, 2011
app pub date -
Jul 7, 2010
filing date -
Jun 15, 2010
priority date (Note) -
Abandoned
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Abstract
A chip package comprises a chip, a plurality of bumps, and a die-attaching tape where the bumps are jointed to the corresponding bonding pads on the active surface of the chip. The die-attaching tape consists of a wiring core, a first dielectric adhesive, and a second dielectric adhesive where the wiring core is sandwiched between the first dielectric adhesive and the second dielectric adhesive. The wiring core is of a thickness of a dielectric material and includes a plurality of conductive traces separated by the dielectric material. The conductive traces are also of the thickness of the dielectric material. The die-attaching tape is attached to the active surface of the chip by the first dielectric adhesive to make the bumps penetrate the first dielectric adhesive and joint to the corresponding conductive traces. Therefore, the die-attaching tape can have both functions of holding the chip and transversely transmitting signals to substrate or another chip to eliminate or reduce the conventional wire-bonding processes.
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