Memory test system with advance features for completed memory system
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 5, 2013
Grant Date -
Dec 8, 2011
app pub date -
Mar 30, 2011
filing date -
Jun 3, 2010
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
In a memory test system with advance features for completed memory system, the hardware components are independently configured to generate versatile test patterns for performing a programmable-loading test, a real case test, and a write-feedback test. The write-feedback test is employed to independently test a memory controller which is embedded in an integrated circuit without communicating with the external SDRAM. In the integrated circuit verification stage, the memory test system supports for analyzing and distinguishing the problems inside or outside of the integrated circuit, and testing individual write and read commands.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully