3D INTEGRATED CIRCUIT SYSTEM AND METHOD

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United States of America Patent

SERIAL NO

13183373

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Abstract

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A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.

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Patent Owner(s)

Patent OwnerAddress
MONTEREY RESEARCH LLC3945 FREEDOM CIRCLE SUITE 900 SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
CHANG, Kuo-Tung Saratoga, US 118 2735
FANG, Shenqing Fremont, US 127 970
KIM, Eunha Menlo Park, US 24 680
MA, Yi Santa Clara, US 122 3864
SUGINO, Rinji San Jose, US 44 534
SUH, YouSeok Cupertino, US 48 185
WAHL, Jeremy Sunnyvale, US 8 107
YANG, Jean Glendale, US 28 440

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