Power Semiconductor Device with Low Parasitic Metal and Package Resistance
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United States of America Patent
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Issued Date -
Oct 6, 2011
app pub date -
Mar 31, 2010
filing date -
Mar 31, 2010
priority date (Note) -
Abandoned
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Abstract
A power semiconductor device includes a semiconductor die with a power transistor on a semiconductor substrate, a plurality of wiring layers vertically spaced apart from one another and the transistor, and a plurality of conductive bumps on each wire of the wiring layer spaced farthest from the substrate. Each wire of the layer closest to the substrate is electrically connected to a terminal of the transistor. The wires of the layer spaced farthest from the substrate extend in generally parallel lines and are electrically connected to a terminal of the transistor through each underlying layer. An additional metal layer having a thickness of at least 50 μm is connected to the die so that contact regions of the additional metal layer are electrically connected to the bumps of the die.
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