Dual Gate LDMOS Device with Reduced Capacitance
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United States of America Patent
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Issued Date -
Oct 6, 2011
app pub date -
Mar 31, 2010
filing date -
Mar 31, 2010
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A transistor includes an n-well implanted in a substrate, a source region including a p-body region in the n-well, and a n+ region and a p+ region in the p-body region, a drain region including a n+ region, and a dual gate between the source region and the drain region. The dual gate includes a first gate on a side closer to the source region and a second gate on a side closer to the drain region, the first gate separated from the second gate by a pre-determined distance sufficient that a capacitance between the gate and the drain is at least 15% lower than a capacitance of a transistor of the same unit cell size and configuration excepting that the first gate and second gate abut.
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