LDMOS Device with P-Body for Reduced Capacitance
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United States of America Patent
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Issued Date -
Oct 6, 2011
app pub date -
Mar 31, 2010
filing date -
Mar 31, 2010
priority date (Note) -
Abandoned
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Abstract
A transistor includes an n-well implanted in a substrate, a source region including a p-body region, a n+ region and a p+ region in the p-body region, a drain region comprising a n+ region, and a gate between the source region and the drain region. The p-body region includes a first implant region having a first depth, a first lateral spread and a first concentration of a p-type impurity, and a second implant region having a second depth, a second lateral spread and a second concentration of the p-type impurity. The second depth is less than the first depth, the second lateral spread is greater than the first lateral spread and the second concentration is greater than the first concentration. The p+ region and n+ region abut the second implant region.
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