PMOS Flash Cell Using Bottom Poly Control Gate
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United States of America Patent
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Issued Date -
Sep 29, 2011
app pub date -
Mar 23, 2010
filing date -
Mar 23, 2010
priority date (Note) -
Abandoned
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Abstract
A two-transistor PMOS memory cell has a selective gate (SG) PMOS and a floating gate (FG) PMOS is provided. A control gate, overlapping the floating gate of the FG PMOS, of the memory cell is made by a polysilicon layer and located on an isolation structure.
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