TESTING METHOD FOR SEMICONDUCTOR MEMORY DEVICE
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United States of America Patent
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Issued Date -
Sep 22, 2011
app pub date -
Mar 22, 2010
filing date -
Mar 22, 2010
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A method comprises simultaneously writing a test bit to a plurality of memory cells in the selected sections of a memory array corresponding to column address signals; individually and successively reading output bits from the memory cells in one of the selected sections of a designated row of the memory array corresponding to column address signals and row address signals; and error-checking the output bits with the test bit, wherein the memory array comprises the plurality of memory cells arranged in rows and columns and the memory cells of each row are divided into a plurality of sections.
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Cited Art Landscape
Patent Citation Ranking
- 6 Citation Count
- G11C Class
- 3.04 % this patent is cited more than
- 14 Age