Secure Anti-Tamper Integrated Layer Security Device Comprising Nano-Structures

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United States of America Patent

APP PUB NO 20110227603A1
SERIAL NO

13045880

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Abstract

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A device and method using one or more electrically conductive nano-structures defined on one or more surfaces of a microelectronic circuit such as an integrated circuit die, microelectronic circuit package a stacked microelectronic circuit package, or on the surface of one or more layers in a stack of layers containing one or more ICs. The nano-structure is in connection with a monitoring circuit and acts as a “trip wire” to detect unauthorized tampering with the device or module. Such a monitoring circuit may include a power source such as an in-circuit or in-module battery and a “zeroization” circuit within the chip or package to erase the contents of a memory when the nano-structure is breached or altered. One or more electrically conductive nano-structures interconnect and reroute one or more electrical connections between one or more ICs to create an “invisible” set of electrical connections on the chip or stack to obfuscate an attempt to reverse engineer the device. microscope.

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Patent Owner(s)

Patent OwnerAddress
PFG IP LLC150 PACIFIC AVENUE SAN FRANCISCO CA 94111

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Boyd, W Eric La Mesa, US 28 755
Leon, John Anaheim, US 32 552
Ozguz, Volkan Aliso Viejo, US 18 787
Yamaguchi, James Laguna Niguel, US 16 153

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