MOS-TYPE ESD PROTECTION DEVICE IN SOI AND MANUFACTURING METHOD THEREOF
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United States of America Patent
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Issued Date -
Sep 15, 2011
app pub date -
Jul 14, 2010
filing date -
Dec 17, 2009
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Abandoned
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Abstract
The present invention discloses a MOS ESD protection device for SOI technology and a manufacturing method for the device. The MOS ESD protection device comprises: an epitaxial silicon layer grown on top of an SOI substrate; a first side-wall spacer disposed on both sides of the epitaxial silicon layer so as to isolate the ESD protection device from the intrinsic active structures; a source region and a drain region disposed respectively on two sides of the epitaxial silicon layer; a poly silicon gate and a gate dielectric formed on top of the epitaxial silicon layer; and a second side-wall spacer disposed on both sides of the poly silicon gate of . ESD leakage current passes down to the SOI substrate for protection. Because ESD protection device and intrinsic MOS transistor are located in the same plane, this fabrication process can be inserted in the current MOS process flow.
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