Methods for Consumption of Timing Margin to Reduce Power Utilization in Integrated Circuitry and Device Implementing the Same
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United States of America Patent
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Issued Date -
Jun 30, 2011
app pub date -
Dec 29, 2010
filing date -
Dec 30, 2009
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Abstract
A circuit is defined to operate in accordance with a common control signal. The circuit includes a plurality of transistors that have respective timing margins relative to the common control signal. Some of the plurality of transistors are defined differently from another of the plurality of transistors with regard to either transistor channel width, transistor channel length, transistor threshold voltage, or a combination thereof. The different definition of any given one of the plurality of transistors causes a reduction of either transistor power consumption, transistor current leakage, or a combination thereof, in exchange for a corresponding reduction in timing margin while maintaining a positive timing margin.
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