Memory and methods of forming the same to enhance scalability of non-volatile two-terminal memory cells
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United States of America Patent
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Issued Date -
Jun 23, 2011
app pub date -
Dec 18, 2009
filing date -
Dec 18, 2009
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Abstract
Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to scale memory elements, such as implemented in BEOL third dimensional memory technology, independent of operational characteristics. In at least some embodiments, a method to fabricate a non-volatile two-terminal memory device includes depositing a first electrode at a first temperature in a first region in relation to a substrate (e.g., a silicon wafer) that includes active circuitry that was previously fabricated FEOL on the substrate, fabricating a memory element coupled to the first electrode, and optionally, forming at least a portion of a non-ohmic device electrically coupled with the memory element. Further, the method can include depositing a second electrode at a second temperature in a second region in relation to the substrate. In some embodiments, the second temperature is approximately equal to or greater than the first temperature.
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