METHOD OF VERTICALLY MOUNTING AN INTEGRATED CIRCUIT
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United States of America Patent
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Issued Date -
Jun 23, 2011
app pub date -
Dec 23, 2009
filing date -
Dec 23, 2009
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A method of mounting a first integrated circuit (102, 500, 704) on one of a circuit board (300, 700) or a second integrated circuit (706), the first integrated circuit (102, 500, 704) formed over a substrate (104) and having a surface (119) opposed to the substrate (104) and a side (122, 530, 930) substantially orthogonal to the surface (119), and including a conductive element (116, 117, 118, 522, 524, 526, 528, 528', 528'') coupled to circuitry (102, 500, 704) and formed within a dielectric material (120, 518), the one of the circuit board (300, 700) or the second integrated circuit (706) including a contact point (304, 306, 314), the method including singulating (1104) the first integrated circuit (102, 500, 704) to expose the conductive element (116, 117, 118, 522, 524, 526, 528, 528', 528'') on the side (222, 630, 1030), and mounting (1108) the first integrated circuit (102, 500, 704) on the one of a circuit board (300, 700) or a second integrated circuit (706) by aligning the conductive element (116, 117, 118, 522, 524, 526, 528, 528', 528'') exposed on the side (222, 630, 1030) to make electrical contact with the contact point (304, 306, 314).
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