Importance

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Abstract

The low voltage mixer circuit can be fitted to a UWB signal transmission device. The circuit includes first and second differential pairs of NMOS transistors (M5, M6, M7, M8), wherein the source of the transistors (M5, M6) of the first pair is connected to the output of a first MOS transistor reverser arrangement (M1, M3) of a transconductance stage, and the source of the transistors (M7, M8) of the second pair is connected to the output of a second MOS transistor reverser arrangement (M2, M4) of the transconductance stage. The drain of the first NMOS transistor (M5) of the first pair and the drain of the second NMOS transistor (M7) of the second pair are connected to a first resistor (R0) for supplying a first output signal (RF0). The drain of the first NMOS transistor (M8) of the second pair and the drain of the second transistor (M6) of the first pair are connected to a second resistor (R1) for supplying a second output signal (RF1). The first and second resistors are connected to the high potential terminal (VDD) of the supply voltage source. The gate of the first NMOS transistors (M5, M8) of the differential pairs receives a first carrier frequency signal (LOP), whereas the gate of the second NMOS transistors (M6, M7) of the differential pairs receives a second carrier frequency signal (LON). A first data signal (IN0) is supplied to the input of the first reverser arrangement (M1, M3), whereas a second data signal (IN1) is supplied to the input of the second reverser arrangement (M2, M4).

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First Claim