Current limit recovery circuit
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United States of America Patent
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Issued Date -
Jun 16, 2011
app pub date -
Dec 14, 2009
filing date -
Dec 14, 2009
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
The present invention provides a synchronous buck switcher including a first loop, second loop, a current limit switch, a capacitor and an RS flip flop. The first loop includes an error amplifier (EA), a pulse width modulator (PWM), a PMOS device and an NMOS device. The second loop includes a second capacitor and a resistor connected between the output terminal of the EA and an input terminal of the EA. During a current limit event, a current limit pulse is applied to the current limit switch which allows the input voltage at the inverting terminal of the EA to follow the decreasing output voltage due to the current limit event. As a result, regulation occurs at this lower voltage at the inverting input of the EA. The inverting input of the EA is then charged back to the original reference voltage, resulting in a smooth recovery from current limit.
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