PWM CONTROLLER WITH LOW UVLO VOLTAGE
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United States of America Patent
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Issued Date -
Jun 2, 2011
app pub date -
Dec 2, 2009
filing date -
Dec 2, 2009
priority date (Note) -
Abandoned
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Abstract
The present invention discloses a PWM controller with low UVLO voltage for switching power applications, having a power supply end coupled to a main input voltage via a resistor and coupled to a ground via a capacitor, and an output end coupled to the gate terminal of a primary side transistor requiring a minimum gate voltage, the PWM controller comprising: a UVLO unit; used for performing a hysteresis comparison of a supply voltage at the power supply end with a UVLO_ON voltage and a UVLO_OFF voltage to generate a control signal, wherein the UVLO_OFF voltage can be as low as the minimum gate voltage; a PWM unit, actuated by the control signal to deliver a PWM signal; and a driving stage, comprising a PMOS transistor having a gate coupled to the PWM signal, a source coupled to the supply voltage and a drain coupled to the output end.
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