Multilayer wiring, method for placing dummy wiring in multilayer wiring, semiconductor device, and semiconductor device manufacturing method
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United States of America Patent
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Issued Date -
Apr 21, 2011
app pub date -
Jun 14, 2010
filing date -
Jun 16, 2009
priority date (Note) -
Abandoned
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Abstract
A multilayer wiring in which plural metal wirings and plural interlayer insulating films are layered, each interlayer insulating film being planarized each time formed, is divided into plural regions. The percentage of an area occupied by each of the metal wirings within each region is obtained for each of the metal wirings. An integral percentage is obtained per region by integrating, the percentages. The integral percentages are used to calculate the relative positional relationship of upper surfaces of the interlayer insulating films of plural regions, from the relative values of the integral percentages obtained beforehand and relative positions of the upper surfaces. In regions where the upper surface is of a height lower than a predetermined value, a dummy wiring is disposed, and in regions where the upper surface is of a height equal to or greater than the predetermined value, a dummy wiring is not disposed.
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