SEMICONDUCTOR CHIP PACKAGES HAVING REDUCED STRESS
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United States of America Patent
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app pub date -
Nov 24, 2010
filing date -
Oct 12, 2007
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Abandoned
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Abstract
A structure. The structure includes (i) a carrier substrate which includes substrate pads, (ii) a chip physically attached to the carrier substrate, and (iii) a first frame physically attached to the carrier substrate. A CTE (coefficient of thermal expansion) of the first frame is substantially lower than a CTE of the carrier substrate.
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