SEMICONDUCTOR DEVICE
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United States of America Patent
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Issued Date -
Feb 24, 2011
app pub date -
Apr 10, 2009
filing date -
Apr 28, 2008
priority date (Note) -
Abandoned
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Abstract
With inversion-mode transistors, intrinsic-mode transistors, or semiconductor-layer accumulation-layer current controlled accumulation-mode transistors, variation in threshold voltages becomes large in miniaturized generations due to statistical variation in impurity atom concentrations and thus it is difficult to maintain the reliability of an LSI. Provided is a bulk current controlled accumulation-mode transistor which is formed by controlling the thickness and the impurity atom concentration of a semiconductor layer so that the thickness of a depletion layer becomes greater than that of the semiconductor layer. For example, by setting the thickness of the semiconductor layer to 100 nm and setting the impurity concentration thereof to be higher than 2.times.10.sup.17 [cm.sup.-3], the standard deviation of variation in threshold values can be made smaller than a power supply voltage-based allowable variation value.
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