Layout design system and layout design method
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United States of America Patent
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Issued Date -
Jan 20, 2011
app pub date -
Jun 29, 2010
filing date -
Jul 16, 2009
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
In a layout design of a semiconductor circuit, by selecting a frequently-used layout cell based on a layout design, a common location (coordinate) at which dummy metal is arranged is specified. A new layout cell in which dummy metal is arranged in advance at the specified arrangement location is generated. Dummy metal is arranged by replacing the frequently-used layout cell from which the new layout cell is generated by the new layout cell having dummy metal or by overlapping them. Thus, process such as wiring correction in which the amount of data depends on processing speed can be carried out by use of the inexpensive computer having low throughputs and the small amount of memory.
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