PARALLEL PROCESSING ARCHITECTURE OF FLASH MEMORY AND METHOD THEREOF
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United States of America Patent
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Issued Date -
Jan 20, 2011
app pub date -
Sep 4, 2009
filing date -
Jul 17, 2009
priority date (Note) -
Abandoned
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Abstract
A parallel processing architecture of flash memory and method thereof are described. A processing unit classifies a plurality of commands to generate a first command group and a second command group respectively. The processing unit executes the first command group and the second command group. A first control unit performs the first command group to access the data stored in the first memory unit, and a second control unit simultaneously performs the second command group to access the data stored in the second memory unit for processing the data stored in the first and the second memory units in parallel.
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