HIV COMBINATION VACCINE AND PRIME BOOST
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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N/A
Issued Date -
Jan 20, 2011
app pub date -
Jan 11, 2008
filing date -
Jan 12, 2007
priority date (Note) -
Abandoned
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Abstract
Provided is a novel, combination prime-boost vaccine against HIV/AIDS that induces long-lasting humoral, cell-mediated and mucosal immune responses against HIV.
First Claim
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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
THE UNIVERSITY OF WESTERN ONTARIO | 1151 RICHMOND STREET NORTH STEVENSON-LAWSON BUILDING ROOM 319 ALEXANDRIA VA 22314 |
International Classification(s)

- 2008 Application Filing Year
- A61K Class
- 9711 Applications Filed
- 5862 Patents Issued To-Date
- 60.37 % Issued To-Date
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Kang, Chil-Yong | London, CA | 14 | 37 |
# of filed Patents : 14 Total Citations : 37 | |||
Michalski, Chad | Rockville, US | 1 | 3 |
# of filed Patents : 1 Total Citations : 3 |
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Patent Citation Ranking
- 3 Citation Count
- A61K Class
- 10.68 % this patent is cited more than
- 14 Age
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Maintenance Fees
Fee | Large entity fee | small entity fee | micro entity fee | due date |
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Fee | Large entity fee | small entity fee | micro entity fee |
---|---|---|---|
Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
Full Text
US Patent Application No: 2008/0030,231
Level Shifter and Voltage Converting Device
Abstract
A level shifter voltage contributing to a simplified interface and realizing a reduced power consumption and a voltage supplying device using such a level shifter are provided. A level shifter (1) receives an input data (Din) having a voltage of 0V (zero) and a clock signal (CLK) to shift said voltage of 0V to 5V. The level shifter (1) comprises a first means for supplying a voltage of Vdd(=5V) to a node (N1) and a second means for supplying a voltage of Vss(=0V) to the node (N1). The second means operates so as to block a supply of the voltage of Vss to the node (N1) when the first means supplies the voltage of Vdd to the node (N1).
Description
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