TESTABLE CIRCUIT WITH INPUT/OUTPUT CELL FOR STANDARD CELL LIBRARY
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United States of America Patent
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Issued Date -
Jan 13, 2011
app pub date -
Jul 9, 2009
filing date -
Jul 9, 2009
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Abandoned
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Abstract
A testable circuit includes a first function logic, an input output cell including an input/output unit and a first control multiplexer; and a first testing block is provided, wherein the input/output unit has at least a connection terminal. The first control multiplexer has an output port coupled to the connection terminal, a first input port coupled to the first functional logic, and a second input port. The first testing block is coupled between the first functional logic and the second input port, wherein when the testable circuit is under a testing mode, the first control multiplexer couples the second input port to the output port; and when the testable circuit is under a normal mode, the first control multiplexer couples the first input port to the output port.
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