Microprocessor communications system
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United States of America Patent
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Issued Date -
Dec 23, 2010
app pub date -
Apr 4, 2008
filing date -
Apr 4, 2008
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A microprocessor communications system utilizes a combination of an activity status monitor register and one or more address select registers to read from a communications port of one processor and write to a communications port of an adjacent processor in a single instruction word loop. This circumvents the requirement to save and retrieve data and/or instructions from memory. A stack register selector contains a plurality of stack registers and a plurality of shift registers, which are interconnected. The stack registers are selected by the shift registers in such a way that the stack registers operate in a circular repeating pattern, which prevents overflow and underflow of stacks.
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