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Abstract

A shared memory is described having a plurality of receive ports and a plurality of transmit ports characterized by a first data rate. A memory includes a plurality of memory banks organized in rows and columns. Operation of the memory array is characterized by a second data rate. Non-blocking receive crossbar circuitry is operable to connect any of the receive ports with any of the memory banks. Non-blocking transmit crossbar circuitry is operable to connect any of the memory banks with any of the transmit ports. Buffering is operable to decouple operation of the receive and transmit ports at the first data rate from operation of the memory array at the second data rate. Scheduling circuitry is configured to control interaction of the ports, crossbar circuitry, and memory array to effect storage and retrieval of frames of data in the shared memory by sequentially querying the plurality of ports for the frames of data, and arbitrating among a subset of the ports having the frames of data to assign starting locations in the memory banks such that the shared memory is fully provisioned for all of the ports simultaneously operating at the maximum port data rate.

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First Claim