PROCESSOR INSTRUCTION GRADUATION TIMEOUT
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United States of America Patent
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N/A
Issued Date -
Dec 16, 2010
app pub date -
Jun 12, 2009
filing date -
Jun 12, 2009
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A multiprocessor computer system comprises a plurality of processors distributed across a plurality of node coupled by a processor interconnect network. One or more of the processors is operable to manage hung processor instructions by setting a graduation timeout counter after a first program instruction graduates, resetting the graduation timeout counter if a subsequent program instruction graduates before the graduation timeout counter expires, and resetting the processor if the graduation timeout counter expires before the subsequent program instruction graduates.
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