CLOCK CIRCUIT FOR DIGITAL CIRCUIT
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United States of America Patent
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Issued Date -
Nov 25, 2010
app pub date -
May 14, 2010
filing date -
May 22, 2009
priority date (Note) -
Abandoned
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Abstract
A method of saving power in a digital circuit driven by a clock running at a rate R, comprising reducing said rate R to a lower rate R′ during periods when said digital circuit is operating at a capacity less than its maximum capacity, and wherein the change from rate R to rate R′ is carried out as a smooth transition.
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