SEMICONDUCTOR MEMORY DEVICE
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United States of America Patent
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Issued Date -
Nov 18, 2010
app pub date -
Jan 19, 2009
filing date -
Jan 22, 2008
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
The semiconductor memory device proposed in the present invention comprises the buffer control circuit which, when writing the data, controls the data input buffer so that the data from the same timing as the clock when the writing command is input is written in the activated memory bank, and which, when reading the data, controls the data output buffer so that the data with the read latency of more than 3 clock cycles after when the reading command is input is read from the activated memory bank.
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