Digital PLL circuit and semiconductor integrated circuit
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Feb 14, 2012
Grant Date -
Oct 21, 2010
app pub date -
Mar 18, 2010
filing date -
Apr 17, 2009
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A digital PLL circuit includes: an oscillation circuit, wherein an oscillation frequency is controlled by changing the number of capacitance elements to be connected in parallel to an inductance element; and a phase comparator part configured to perform a digital phase comparison of a reference clock and a delayed clock thereof, with an oscillation circuit output; and based on the comparison result, to control the number of the capacitance elements so as to bring the phase of the oscillation circuit output closer to the reference clock phase, wherein the capacitance element includes: a coarse adjustment capacitor configured to have a predetermined capacitance; and fine adjustment capacitors configured to have a capacitance of 1/n of that of the coarse adjustment capacitor, wherein a predetermined number of the fine adjustment capacitors function as one coarse adjustment capacitor at the time of coarse adjustment.
First Claim
Family
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully