STRUCTURE AND FABRICATING PROCESS OF NON-VOLATILE MEMORY

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United States of America Patent

APP PUB NO 20100252875A1
SERIAL NO

12417639

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Abstract

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A structure of a non-volatile memory is described, including a substrate, isolation structures disposed in and protrudent over the substrate, floating gates as conductive spacers on the sidewalls of the isolation structures protrudent over the substrate, and a tunneling layer between each floating gate and the substrate. A process for fabricating a non-volatile memory is also described. Isolation structures are formed in a substrate protrudent over the same, a tunneling layer is formed over the substrate, and then floating gates are formed as conductive spacers on the sidewalls of the first isolation structures protrudent over the substrate.

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Patent Owner(s)

Patent OwnerAddress
POWERCHIP SEMICONDUCTOR CORPNO 12 LI-HSIN RD I SCIENCE-BASED INDUSTRIAL PARK HSIN-CHU CITY

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Shirota, Riichiro Kanagawa, JP 208 7211

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