Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit may include a memory array with a plurality of memory cells, first logic circuitry, first switching circuitry, first latch circuitry, and second switching circuitry. The first logic circuitry may be configured to generate a first bit line pre-charge signal for a first memory cell of the plurality of memory cells, where the first bit line pre-charge signal is generated in response to a sleep signal. The first switching circuitry may be configured to provide power to one or more bit line of the first memory cell in response to the first bit line pre-charge signal. The first latch circuit may receive the sleep signal and the first bit line pre-charge signal and generate a delayed sleep signal. The second logic circuitry may be configured to generate a second bit line pre-charge signal for a second memory cell of the plurality of memory cells, where the second bit line pre-charge signal is generated in response to the delayed sleep signal. The second switching circuitry may be configured to provide power to one or more bit line of the second memory cell in response to the second bit line pre-charge signal.

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