METHOD AND MACHINE FOR EXAMINING WAFERS
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United States of America Patent
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N/A
Issued Date -
Aug 19, 2010
app pub date -
Feb 13, 2009
filing date -
Feb 13, 2009
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
Method and machine utilizes the real-time recipe to examine a series of wafers during the fabrication of integrated circuits. Each real-time recipe essentially corresponds to a practical fabrication history of a wafer to be examined and/or the examination results of at least one examined wafer of same “lot”. Therefore, different wafers can be examined by using different recipes where each recipe corresponds to a specific condition of a wafer to be examined, even these wafers are received by a machine for examining at the same time.
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Cited Art Landscape
Patent Citation Ranking
- 2 Citation Count
- G06F Class
- 1.58 % this patent is cited more than
- 15 Age