Method and Apparatus for Small Die Low Power System-on-chip Design with Intelligent Power Supply Chip
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United States of America Patent
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N/A
Issued Date -
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app pub date -
May 3, 2010
filing date -
Apr 20, 2007
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A method and system of system-on-chip design that provides the benefits of reduced design time, a smaller die size, lower power consumption, and reduced costs in chip design and production. The process seeks to remove the worst performance and worst power case scenarios from the design and application phases. This is accomplished by planning the power supply voltage in the design phase along with its tolerance with process corner and temperature combinations. The established plan is then applied with communications between power supply integrated circuits and load system-on-chip.
First Claim
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Family
Country | kind | publication No. | Filing Date | Type | Sub-Type |
---|---|---|---|---|---|
US | B2 | US7739626 | Apr 20, 2007 | Patent | Grant |
Type : Patent Sub-Type : Grant | |||||
GRANTED PATENT AS SECOND PUBLICATION | Method and apparatus for small die low power system-on-chip design with intelligent power supply chip | Jun 15, 2010 | |||
CN | A | CN101663815 | Apr 15, 2008 | Patent | Application |
Type : Patent Sub-Type : Application | |||||
UNEXAMINED APPLICATION FOR A PATENT FOR INV. | Method and apparatus for small die low power system-on-chip design with intelligent power supply chip | Mar 03, 2010 | |||
WO | A1 | WO2008130938 | Apr 15, 2008 | Patent | Application |
Type : Patent Sub-Type : Application | |||||
INTERNATIONAL APPLICATION PUBLISHED WITH INTERNATIONAL SEARCH REPORT | METHOD AND APPARATUS FOR SMALL DIE LOW POWER SYSTEM-ON-CHIP DESIGN WITH INTELLIGENT POWER SUPPLY CHIP | Oct 30, 2008 | |||
TW | A | TW200907729 | Apr 18, 2008 | Patent | Application |
Type : Patent Sub-Type : Application | |||||
LAID OPEN APPLICATION FOR PATENT OR PATENT OF ADDITION | Method and apparatus for small die low power system-on-chip design with intelligent power supply chip | Feb 16, 2009 |
- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
DIALOG SEMICONDUCTOR INC | 675 CAMPBELL TECHNOLOGY PARKWAY SUITE 150 CAMPBELL CA 95008 |
International Classification(s)

- 2010 Application Filing Year
- G01R Class
- 3671 Applications Filed
- 2520 Patents Issued To-Date
- 68.65 % Issued To-Date
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
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Jin, Xuecheng | Palo Alto, US | 21 | 616 |
# of filed Patents : 21 Total Citations : 616 | |||
Kesterson, John W | San Jose, US | 14 | 584 |
# of filed Patents : 14 Total Citations : 584 | |||
Malinin, Andrey B | Fort Collins, US | 12 | 149 |
# of filed Patents : 12 Total Citations : 149 |
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Patent Citation Ranking
- 2 Citation Count
- G01R Class
- 3.56 % this patent is cited more than
- 15 Age
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Maintenance Fees
Fee | Large entity fee | small entity fee | micro entity fee | due date |
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Fee | Large entity fee | small entity fee | micro entity fee |
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Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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