Method and Apparatus for Small Die Low Power System-on-chip Design with Intelligent Power Supply Chip

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United States of America Patent

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12772803

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Abstract

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A method and system of system-on-chip design that provides the benefits of reduced design time, a smaller die size, lower power consumption, and reduced costs in chip design and production. The process seeks to remove the worst performance and worst power case scenarios from the design and application phases. This is accomplished by planning the power supply voltage in the design phase along with its tolerance with process corner and temperature combinations. The established plan is then applied with communications between power supply integrated circuits and load system-on-chip.

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DIALOG SEMICONDUCTOR INC675 CAMPBELL TECHNOLOGY PARKWAY SUITE 150 CAMPBELL CA 95008

International Classification(s)

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  • 2010 Application Filing Year
  • G01R Class
  • 3671 Applications Filed
  • 2520 Patents Issued To-Date
  • 68.65 % Issued To-Date
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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Jin, Xuecheng Palo Alto, US 21 616
Kesterson, John W San Jose, US 14 584
Malinin, Andrey B Fort Collins, US 12 149

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  • 2 Citation Count
  • G01R Class
  • 3.56 % this patent is cited more than
  • 15 Age
Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges3448023185352518126481701 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +0255075100125150175200225250275300325350375400425450475500525

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