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Abstract

A frequency divider circuit includes: a shift register capable of storing at least n-bit data configured to shift an input signal sequentially in synchronization with a clock signal; a pulse generating circuit configured to change the input signal into a pulse form in response to a change in logic level of an output signal from a stage of the shift register among n-bit output signals from the shift register, the stage corresponding to a bit resulting from shifting of the input signal by n bits; and a frequency dividing signal generating circuit configured to generate a frequency dividing signal whose logic level is inverted in response to a change in logic level of an output signal from any one stage of the shift register or logic level of the input signal, in order to divide the clock signal in frequency by a dividing ratio corresponding to the n bits.

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First Claim