Fault Current Limiter
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United States of America Patent
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Issued Date -
Jul 29, 2010
app pub date -
Jul 9, 2007
filing date -
Jul 9, 2007
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A method is for suppressing induced steady state and transient currents and voltages in the DC circuit and coil of a magnetically saturated core fault current limiter. The method includes the steps of: (a) providing a first current coil connected to a DC power source surrounding the core for magnetically saturating the core; and (b) providing a second resistive current coil surrounding the core and either short circuited or interconnected to the DC power source in parallel to the first current coil and wound around the core in a forward or reverse sense to the first current coil.
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