APPARATUS COMPRISING A PLURALITY OF ARITHMETIC LOGIC UNITS
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United States of America Patent
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Issued Date -
Jul 15, 2010
app pub date -
Dec 18, 2009
filing date -
Jan 9, 2009
priority date (Note) -
Abandoned
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Abstract
An arrangement of arithmetic logic units carries out an operation on at least one operand, wherein the operation is determined by operation codes received by the arithmetic logic units. The operation codes and at least one operand are received on a first clock cycle. The result of the operation is output from at least one arithmetic logic unit to at least one further arithmetic logic unit. A result of the plurality of arithmetic logic units is then output on a next clock cycle.
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